Flip-flop

ABSTRACT

A flip-flop, comprising a pair of inverter stages including Nchannel MOS field effect transistors serving as switching elements, the pair of inverter stages being cross coupled to each other so as to assume two stable switching states, steering gate circuits adapted to sense the switching states of each of the inverter stages, and switching circuits for changing one switching state sensed by the gate circuits to the other switching state, wherein each of the steering gate circuits is constituted by a P-channel MOS field effect transistor connected with the output terminal of one of the inverter stages and an Nchannel MOS FET connected in series with the P-channel FET, the input terminal is connected with the P-channel FET&#39;&#39;s, and the output terminal of the other inverter stage is connected with the N-channel FET&#39;&#39;s.

United States Patent OTHER REFERENCES IBM Technical Disclosure Bulletin, Vol. 9, No. 4, September 1966, pp 420 & 421, tilted Memory Cell With Low Standby Power," written by G. C. Feth. A copy is located in class 307, subclass 279 in Art Unit 254.

Primary Examiner-Stanley T. Krawczewicz Attorney-Craig, Antonelli, Stewart & Hill ABSTRACT: A flip-flop, comprising a pair of inverter stages including N-channel MOS field effect transistors serving as switching elements, the pair of inverter stages being cross coupled to each other so as to assume two stable switching states, steering gate circuits adapted to sense the switching states of each of the inverter stages, and switching circuits for changing one switching state sensed by the gate circuits to the other switching state, wherein each of the steering gate circuits is constituted by a P-channel MOS field effect transistor connected with the output terminal of one of the inverter stages and an N-channel MOS FET connected in series with the P- channel F ET, the input terminal is connected with the P-channel FETs, and the output terminal of the other inverter stage is connected with the N-channel FETs lnventor Minoru Hujita Kodaira-Shi, Japan Appl. No. 764,428 Filed Oct. 2, 1968 Patented Jan. 12, 1971 Assignee Hitachi, Ltd.

Chiyoda-ku, Tokyo, Japan a corporation of Japan Priority Oct. 16, 1967 Japan 42/66133 FLIP-FLOP 5 Claims, 11 Drawing Figs.

US. Cl 307/279, 307/225, 307/246, 307/304 Int. Cl H03k 3/286 Field of Search 307/279, 205, 251, 291, 304, 246, 225

References Cited FOREIGN PATENTS 1,113,140 5/1968 Great Britain 307/279 'PATENIED JAN 1 2197! saw 2 [IF 3 Dal bur rtrr-rror This invention relates to a flip-flop using insulated gate-type field effect transistors.

It is well known in the art to construct a flip-flop for performing binary-counting action by the use of insulated gatetype or MIS-(Metal Insulator Semiconductor) type field effect transistors (referred to simply as MIS transistor hereinafter). In such flip-fiop, the gate capacitance of an MIS transistor is utilized as element for temporarily storing information. Thus, the flip-flop of the aforementioned type is advantageous over a binary counter flip-flop using bipolar transistors in that the number of circuit elements can be greatly reduced and power consumption can be lowered, and it is advantageous particularly in that the manufacture thereof can be facilitated when it is constructed in the form of a semiconductor integrated circuit, since it is constituted by MIS transistors.

Such flip-flop is disclosed in the US Pat. No. 3,363,l 15, for example. Another example will be described with reference to the drawings.

Considering the breakdown voltage of an MIS transistor, variation of power source voltage V and power consumption in the semiconductor integrated circuit arrangement, it is desirable that such flip-flop be operated at a low voltage. That is, if the flip-flop can be operated by means of a low-voltage source, then variation of the DC power source voltage V becomes noncritical, since the upper limit of the power source voltage for the flip-flop is determined by the breakdown voltage of the MIS transistor. Thus, the power source V can be constituted by dry cells, and no stabilized power source device is needed.

Because of low-power source voltage, the on current flowing through MIS transistor is decreased, which leads to less power consumption in the flip-flop per se. This is advantageous in that heat generation in the semiconductor integrated circuit arrangement can be minimized. Particularly in an attempt to construct a counter comprising a number of such flip-flops in a single semiconductor substrate by the integrated circuit technique, it is essential that power consumption be minimized to prevent heat generation.

In the conventional flip-flop, on the other hand, an input pulse signal voltage V for driving steering gate MIS transistors should be high, and therefore the power source voltage V should also be high.

It is an object of the present invention to provide a flip-flop which can be operated by a low-voltage source and is constituted by MTS transistors.

Another object of the present invention is to provide a flipflop suited to construct a counter (flip-flop chain) which is capable of achieving the desired counting action.

Still another object of the present invention is to provide a flip-flop which can easily be produced by the semiconductor integrated circuit technique.

in accordance with an embodiment of the present invention, there is provided a flip-flop comprising first and second switching stages or inverter stages which are cross coupled to each other, said first and second switching stages or inverter stages being constituted by first and second MIS or MOS Metal-Oxide-Semiconductor) transistors in such a manner as to assume two stable switching states, first and second steering gate circuits connected with the first and second switching stages to sense the switching states of the latter respectively, and first and second switching circuits connected between the gate circuits and the first and second switching stages to change the switching state of the switching stages from one stable state sensed by the gate circuits to the other stable state. The two steering gate circuits are constituted by third and fourth MIS transistors connected with the output terminals of the first and second switching stages respectively, and fifth and sixth MIS transistors connected in series with the third and fourth transistors respectively. The third and fourth MIS transistors are connected with first and second input terminals respectively, and the fifth and sixth MIS transistors are connected with the output terminals of the second and first switching stages respectively. The switching circuits are constituted by MIS transistors which receive as input thereto the output of the steering gate circuits to temporarily memorize the state of the flip-flop. The third MIS transistor and the fifth MIS transistor are complementary to each omen-Le opposite to each other in respect of channel-conductivity ype, as is the case with the fourth and sixth transistors. In short, the novel feature of the flip-flop embodying the present invention resides in that two complementary MlS,transistors are connected in series with the circuits between the sources and the drains of inverter transistors, and that the outputs of the gate circuits are imparted to the memory MIS transistors as inputs.

Thus, the input pulse signal may be of single phase, and the input pulse signal. voltage may be low. In addition, such circuit arrangement can easily be constructed in the form of a semiconductor integrated circuit, since it is constituted by MIS or MOS transistors.

Other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction .with. the accompanying drawings, in

which: r r.

FIG. 1 is a circuit diagram showing a conventional flip-flop;

FIGS. 2a to 2d are views showing waveforms useful for explaining the operation of the flip-flop shown in FIG. 1;

FIG. 3 is a block diagram showing a flip-flop chain wherein a plurality of flip-flops are connected in cascade with each other;

FIG. 4 is a circuit diagram showing the flip-flop according to an embodiment of the present invention;

FIGS. 5a and 5b are views showing waveforms useful for explaining the operation of the flip-flop shown in FIG. 4;

FIG. 6 is a flip-flop according to a second embodiment of the present invention; and

FIG. 7 is a circuit diagram showing part of the flip-flop according to a third embodiment of the present invention.

Referring first to FIG. 1, T and T represent inverter MIS transistors, and T and T load MIS transistors of which the drain electrodes are connected with a DC power source ter minal P. T and '1' denote control MIS transistors of which the gate electrodes are connected with an input pulse signal terminal 1],. T and T indicate storage M IS transistors adapted for producing storing effect in accordance with the gate capacitance thereof, and T and T, steering gate MIS transistors of which the gate electrodes are coupled to an input pulse signal terminal i By applying pulse signals out of phase with each other such as shown in FIGS. 2a and 2b to the pulse signal input terminals i and 1}, respectively, it is possible to obtain at output terminals 0,, and 0,, output pulse signals of which the frequency is half the input pulse signal frequency as shown in FIGS. 2a and 217, respectively. Thus, this flip-flop is enabled to produce binary-counting action.

The insulated gate MIS transistors T, and T,, have their source electrodes connected with the gate electrodes of the storage MIS transistors T and T Hence, when the gate capacitances of the storage MIS transistors T and T are negatively charged, the gate voltage (referred to as threshold voltage) to render the gate MIS transistors T and T conductive remains unchanged with respect to the source voltage, but the gate voltage to turn on the transistors T and T relative to the earth potential becomes negatively higher (--l5 v., for example) than the threshold voltage (-6 v., for example) of the transistor T Thus, it is necessary to use a high negative voltage (-20 v., for example) as input pulse signal voltage v,

On the other hand, the gate voltage (voltage between the gate and the source) of the control MIS transistors T and T is available from the'input pulse signal voltage source through the paths between the sources and drains of the memory MIS transistors T and T The control MIS transistors T and '1], are rendered conductive only when the memory MIS transistors T and T; are turned on, so that the voltage of the voltage source 7 may be lower than that of the voltage source V (halfthe voltage of the voltage source V for example).

As described above, in the conventional flip-flop circuit, the input pulse signal voltage V may be low, but the input pulse signal voltage V, should be high.

In an attempt to construct 2" -counter by connecting n such flip-flops in cascade with each other as shown in FIG. 3, it is necessary to use a high-power source voltage V,,,, (--30 v., for example). since the pulse signal voltage V applied to the input pulse signal terminal 1' of a succeeding flip-flop should be high (the output pulse voltage V at the output terminal of the flip-flop should be high).

Description will now be made of an embodiment of the present invention with reference to FIG. 4.

Referring to FIG. 4, T and T represent inverter MIS transistors, and T and T' load MIS transistors of which the drain electrodes as well as the gate electrodes are connected with the power source terminal P. T and T indicate control MIS transistors of which the gate electrodes are connected with the input pulse signal terminal i. T, and T denote memory MIS transistors for producing a memory effect with the aid of their gate capacitances C and C,,. A pair of switching circuits are constituted by the transistors T T and T',;,, T,,, respectively. T and T represent first and second steering gate MIS transistors of which the gate electrodes are connected with the drain electrodes of the inverter MIS transistors T and T respectively. As the inverter MIS transistors, control MIS transistors, memory MIS transistors and first and second steering gate MIS transistors, use is made of P-channel enhancement MOS FETs. Further, as T and T' use is made of N-channel enhancement MOS FETs whose channel is of the opposite conductivity type to that of the gate MIS transistors T and T namely, N-channel. The

P-channel and N-channel MOS FETs may be formed in a silicon substrate by the conventional selective diffusion technique. Each of the pair of switching circuits is adapted to memorize and control the flip-flop conditions through the first and second steering gate transistors, respectively. T and T represent third and fourth steering gate MIS transistors having the gates thereof connected with the pulse signal input terminal 1'.

The DC voltage .Vm, is applied to the power source terminal P, and such a pulse signal as shown in FIG. 5a is imparted to the pulse signal input terminal i.

Thus, it is possible to obtain at the terminal 0,, (or 0,,) an output pulse signal V (or V of which the frequency is half the frequency of the input pulse signal as shown in FIG. 5b.

In order to give better understanding of the present invention, the circuit operation will be described with reference to FIG. 5.

Assume that the input pulse signal voltage V, is a reference potential (O-level) during the period of time from O to 2 to render T nonconductive (T, conductive) so that V becomes approximately -E volts (l-Ievel). Then, since T' is in the conducting state, V becomes approximately equal to the reference voltage, and T is rendered noncon ductive. On the other hand, T is in the conducting state. At this point, T and T', are rendered conductive and T and T nonconductive by the input pulse signal voltage V1.\-, so that the gate capacitance C,, of T is charged up to the voltage of E volts through the passage between the source and the gate of T Thus, T is rendered conductive, while T remains nonconductive since the gate voltage thereof becomes zero.

Next, consider the range from t, to t where the input pulse signal voltage is E, volts. In thetransient state occurring at and around the point of time t,, T and T are rendered nonconductive momentarily when the point of time t is reached, but T remains in the previous state or conducting state due to the voltage stored in the gate capacitance thereof. On the other hand, T is maintained in the nonconducting state. T and T are momentarily rendered conductive at the point of time t,. Thus, in the transient state, the drain voltage of T (hence the gate voltage of T becomes substantially zero so that T is rendered nonconductive while T is rendered conductive. This is reversal of the state occurring between the points of time 0 and 1,. In the steady state subsequent to the reversal of state, T is rendered conductive so that T is made nonconductive. Further, since T is in the conductive state, T is rendered nonconductive, and T' is still maintained in the nonconducting state.

In this way, the inverter MIS transistors are supplied with the input pulse signals, and when both the memory M IS transistors and the control MIS transistors are rendered conductive, the state of the flip-flop is reversed. Thus, the flip-flop is returned to the original state at every second input pulse signal.

Tables I and 2 show changes of the state of each transistor with time, from which the operation of this invention will be more readily appreciated. In these tables, the state indicated in the upper frame at each point of time indicates a transient state which occurs momentarily upon change of the input pulse signal, and the state indicated in the lower frame shows a steady state occurring at that point of time. For example, in the column corresponding to the period between the points of time t and t on" is indicated in the upper frame and off in the lower frame for T This means that in the transient state occurring at the point of time t,, T is in the conducting state, and it is rendered nonconductive in the steady state wherein the inverter transistors are reversed, as described above.

As will be seen from tables 1 and 2, it is when the memory MIS transistor T (or T', and control MIS transistor T (or T, are simultaneously rendered conductive that the state of the flip-flop is reversed.

Thus, the gate voltage to render the control MIS transistors conductive can be maintained at a low value (6 v., for example) with respect to the earth potential without being affected by the memory MIS transistors, so that the maximum value E volts of the input pulse signal V, can be made close to the threshold voltage of the control MIS transistor (-7 v., for example).

The MIS transistor T (or T',,) is adapted to turn on only when the input pulse signal V, is zero volt (reference potential) so that the inverter MIS transistor T (or T',,) is rendered nonconductive. Thus, the threshold voltage of T (or T is available directly from the drain voltage of the inverter transistor T (or T', Consequently, the gate voltage relative to the earth potential to render T or T' conductive is made substantially equal to the threshold voltage'of T (or T',,) without being influenced by the other transistors, as in the conventional case.

The result is that the power source voltage V,,,, determining the drain voltage of the inverter MIS transistor when the latter is in the nonconductive state can be made low (-14 v., for example).

Thus, in accordance with the present invention, the l-level voltages -E, and E, for the input pulse signal voltage V, and output pulse signal voltage V can be made equal, and yet they can be made low. This makes it possible to realize a cascaded connection of multiple flip-flops (flip-flop chain) without increasing the power source voltage as in the prior art.

Furthermore, in accordance with the present invention, a binary-counting action can be produced merely by the use of a single-phase input pulse signal voltage, and therefore a flipflop chain such as shown in FIG. 3 can be realized by connecting the output terminal directly with the pulse signal input terminal of a succeeding flip-flop.

FIG. 6 shows another embodiment of the present invention, wherein parts representing the same functions as those of FIG.

4 are represented by similar symbols.

This flip-flop is differentfrom the FIG. 4 arrangement in that the path between the source and the drain of the control MIS transistor T" is connected in series with the paths between the sources and drains of the memory MIS transistors T and T', With such a circuit arrangement, it is possible to perform the same operation as that of the FIG. 4 circuit ar- 'rangement described above.

In the foregoing flip-flops of the present invention, N-channel enhancement mode MIS FETs were used as the gate transistors (T and T', and P-channel enhancement mode MIS FETs as the remaining transistors. However, this invention is not limited to such cases, but it can equally be applied to the cases where use is made of P-channel MIS FETs as the gate transistors and N-channel MIS FET's as the remaining transistors. In the latter cases, pulse signals to be handled are naturally limited to those which change in the positive direction with respect to the reference voltage. Although description has been made of the case where the load MIS transistors were indentical in channel conductivity type with the inverter MIS transistors, it is possible that resistance elements are constituted by transistors of opposite conductivity type to that of the inverter MIS transistors. In this case, the load MIS transistors T and T' are connected, for example,

' as shown in FIG. 7.

Iclaim: l. A flip-flop, comprising first and second switching stages including:

first and second insulated gate field effect transistors serving as switching elements, the inputs and outputs of said two switching stages being cross coupled to each other so that said two switching stages constitute a bistable switching circuit; first and second steering gate circuits connected with said first and second switching stages, respectively, to sense the switching states of said switching stages, said first gate circuit being constituted by a third insulated gate field effect transistor having a channel of a first conductivity type and a fourth insulated gate field effect transistor having a channel of a second conductivity type which is connected in series with said third transistor, said second gate circuit being formed by a fifth insulated gate ,field effect transistor having a channel of the first conductivity type and a sixth insulated gate field effect transistor having a channel of the second conductivity type which isconnected in series with said fifth transistor;

first and second switching circuit means for changing said switching states of said switching stages from one stable switching state sensed by the steering gate circuits to the other stable switching state, said first switching means being connected with said first switching stage and said first steering gate circuit, said second switching means being connected with said second switching stage and said second steering gate circuit;

input terminals connected with said third and fifth insulated gate field effect transistors and said first and second switching circuits;

means for connecting the output of the first switching stage to the gate of said sixth transistor; and

means for connecting the output of the second switching means to the gate of said fourth transistor.

2. A flip-flop as set forth in claim 1, wherein said third and fifth insulated gate field effect transistors are of N-channel enhancement mode, and said fourth and sixth insulated gate field effect transistors are of P-channel enhancement mode.

3. A flip-flop, comprising a first insulated gate-type field effect transistor of a first conductivity type having the drain thereof connected with a DC power source through a first resistance element and the source thereof connected with a reference potential source; a second insulated gate type of the first conductivity type having the drain thereof connected with the gate of said first field effect transistor and withthe DC power source through a second resistance element, the gate and source of said second field effect transistor being connected with the drain of said first field effect transistor and said reference potential source respectively; a third insulated gate-type field effect transistor of second conductivity type having the source thereof connected with the drain of said first field effect transistor and the gate thereof connected, with a pulse input terminal; a fourth insulated gate field effect transistor of the second conductivity type having the source thereof connected with the drain of said second field effect transistor and the gate thereof connected with said pulseinput terminal; a fifth insulated gate field effect transistor of the first conductivity type having the drain thereof connected with the drain of said third field effect transistor and the gate thereof connected with the drain of said second field effect transistor and the source thereof connected with the reference potential source; a sixth field effect transistor of the first conductivity type the drain, source and gate of which are connectedwith the drain of said fourth field effect transistor, said reference potential source and the drain of said first field effect transistor respectively; a seventh insulated gate field effect transitor having the passage between the source and thedrain thereof connected in parallel with the passage between the source and the drain of said first field effect transistor through the passage between the source and the drain of a controlinsulated gate field effect transistor of the first conductivity type, the gate of said seventh transistorbeing connected with the drain of said fifth field effect transistor; and aneighth insulated gate field effect transistor having the. passage between .the source and the drain thereof connected in parallel with the passage between the source andthe drain of saidsecond field effect transistor through the passage betweenthe source and the drain of said control insulated gate field effect transistor being connected with the drain of said sixth field effect transistor, the gate of saidcontrol field effect transistor being connected with said pulse input terminal.

, 4. A flip-flop as set forth in claim 3, wherein first and second insulated gate field effect transistors, of the first conductivity type are used instead of said control transistor, the passage input terminal.

5. A flip-flop as set forth in claim 3, wherein insulated gate field effect transistors are utilized as said first and second resistance elements. 

1. A flip-flop, comprising first and second switching stages including: first and second insulated gate field effect transistors serving as switching elements, the inputs and outputs of said two switching stages being cross coupled to each other so that said two switching stages constitute a bistable switching circuit; first and second steering gate circuits connected with said first and second switching stages, respectively, to sense the switching states of said switching stages, said first gate circuit being constituted by a third insulated gate field effect transistor having a channel of a first conductivity type and a fourth insulated gate field effect transistor having a channel of a second conductivity type which is connected in series with said third transistor, said second gate circuit being formed by a fifth insulated gate field effect transistor having a channel of the first conductivity type and a sixth insulated gate field effect transistor having a channel of the second conductivity type which is connected in series with said fifth transistor; first and second switching circuit means for changing said switching states of said switching stages from one stable switching state sensed by the steering gate circuits to the other stable switching state, said first switching means being connected with said first switching stage and said first steering gate circuit, said second switching means being connected with said second switching stage and said second steering gate circuit; input terminals connected with said third and fifth insulated gate field effect transistors and said first and second switching circuits; means for connecting the output of the first switching stage to the gate of said sixth transistor; and means for connecting the output of the second switching means to the gate of said fourth transistor.
 2. A flip-flop as set forth in claim 1, wherein said third and fifth insulated gate field effect transistors are of N-channel enhancement mode, and said fourth and sixth insulated gate field effect transistors are of P-channel enhancement mode.
 3. A flip-flop, comprising a first insulated gate-type field effect transistor of a first conductivity type having the drain thereof connected with a DC power source through a first resistance element and the source thereof connected with a reference potential source; a second insulated gate type of the first conductivity type having the drain thereof connected with the gate of said first field effect transistor and with the DC power source through a second resistance element, the gate and source of said second field effect transistor being connected with the drain of said first field effect transistor and said reference potential source respectively; a third insulated gate-type field effect transistor of second condUctivity type having the source thereof connected with the drain of said first field effect transistor and the gate thereof connected with a pulse input terminal; a fourth insulated gate field effect transistor of the second conductivity type having the source thereof connected with the drain of said second field effect transistor and the gate thereof connected with said pulse input terminal; a fifth insulated gate field effect transistor of the first conductivity type having the drain thereof connected with the drain of said third field effect transistor and the gate thereof connected with the drain of said second field effect transistor and the source thereof connected with the reference potential source; a sixth field effect transistor of the first conductivity type the drain, source and gate of which are connected with the drain of said fourth field effect transistor, said reference potential source and the drain of said first field effect transistor respectively; a seventh insulated gate field effect transitor having the passage between the source and the drain thereof connected in parallel with the passage between the source and the drain of said first field effect transistor through the passage between the source and the drain of a control insulated gate field effect transistor of the first conductivity type, the gate of said seventh transistor being connected with the drain of said fifth field effect transistor; and an eighth insulated gate field effect transistor having the passage between the source and the drain thereof connected in parallel with the passage between the source and the drain of said second field effect transistor through the passage between the source and the drain of said control insulated gate field effect transistor being connected with the drain of said sixth field effect transistor, the gate of said control field effect transistor being connected with said pulse input terminal.
 4. A flip-flop as set forth in claim 3, wherein first and second insulated gate field effect transistors of the first conductivity type are used instead of said control transistor, the passage between the source and the drain of said first control field effect transistor is connected in series with that of said seventh transistor, the passage between the source and the drain of said second control field effect transistor is connected in series with that of said eighth transistor, and the gates of said first and second control transistors are connected with said pulse input terminal.
 5. A flip-flop as set forth in claim 3, wherein insulated gate field effect transistors are utilized as said first and second resistance elements. 